1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to an improvement of a nonvolatile memory using a multilayer type transistor as memory cells.
2. Description of the Related Art
Demands for large-capacity semiconductor memories and high-speed semiconductor devices have been increasing in recent years. A semiconductor device using a nonvolatile memory, EEPROM, which uses an insulating film sandwiched between a floating gate electrode and a control gate electrode as a capacitance for data storage, is not an exception.
Representative types of EEPROMs are a channel erase type and a source erase type. In the channel erase type, data is erased by an F-N (Fowler-Nordheim) current flowing between a gate electrode and an entire channel region formed between a source and a drain. In the source erase type, data is erased by the F-N current flowing between a source diffusion layer and a gate electrode edge on the side of the source diffusion layer. To satisfy the demands for the large memory capacity and the high-speed operation simultaneously, generally used is the source erase type, since data can be erased at a lower voltage.
Hereinbelow, we will describe a nonvolatile memory of the prior art which employs multilayer gate transistors as a memory cell, by taking a flash EEPROM of the source-erase type as an example and referring to accompanying drawings.
To ensure the reliability of memory cells of a conventionally employed source-erase type flash EEPROM, a double diffusion layer made of phosphorus and arsenic is sometimes employed for the purpose of forming a deep source diffusion layer, as is described in Jpn. Pat. Appln. KOKOKU Publication No. 6-082841.
The phosphorus deeply diffused in the source diffusion layer plays an important role in ensuring the reliability as described below. During the data-erase operation, the deeply-diffused phosphorus is responsible for reducing an electric-field component parallel to the interface between the semiconductor substrate and the tunnel oxide film, thereby preventing the generation of the tunnel current between bands, which would cause an excessive erase and a nonuniform erase. This role of phosphorus is described on page 56-57 of "Flash Memory Technical Handbook" published by Science Forum.
However, since the concentration of diffused phosphorus required for attaining the reliability is relatively high, it is difficult to form a narrow tunnel region. This is one of the obstacles to miniaturization of memory cells. In this circumstance, the demand for the miniaturization has been fulfilled by the SAS (self-aligned source) technology, more specifically, the techniques disclosed in U.S. Pat. No. 4,500,899 and in U.S. Pat. No. 5,019,527, in combination.
FIGS. 2 to 7 are views for explaining a conventional memory device. FIGS. 2A, 3A, 4A 5A and 6A are cross sectional views taken along the line a--a which crosses a word line of the memory cell at a right angle. On the other hand, FIGS. 2B, 3B, 4B, 5B and 6B are cross sectional views taken along the line b--b drawn almost at a center of the region sandwiched between adjacent memory cells with no floating gate electrode and crossing the word line at a right angle (hereinafter, this region will be referred to as "cell slit"). FIG. 7 is a magnified view of a portion 215 shown in FIG. 6A.
As shown in FIGS. 2A and 2B, on a P-type silicon substrate 201, a P-layer 202 for preventing field inversion and a field oxide film 203 are provided. On the region of the P-type silicon substrate 201 excluding the field oxide film 203, a tunnel oxide film 204 (hereinafter referred to as "first gate insulating film") is provided. On the first gate insulating film 204, a floating gate electrode 205, an ONO (SiO.sub.2 /Si.sub.x N.sub.y /SiO.sub.2) film 207 (hereinafter referred to as "second insulating film"), a control gate electrode 208 are formed in a sequential manner. Thereafter, a photo resist 210 is formed on the region excluding at least the source diffusion layer and a diffusion layer for wiring between source diffusion layers (hereinafter referred to as "source wiring region").
Next, as shown in FIGS. 3A and 3B, the first gate insulating film 204 and the field oxide film 203 on the source diffusion layer and the source wiring layer are removed by etching and then the resist pattern 210 is removed. Thereafter, a post oxide film 211 is formed and then a photo resist 212 is formed on the area excluding the source diffusion layer and source wiring region.
Further, as shown in FIGS. 4A and 4B, using the resist pattern 212 as a mask, phosphorus ions are implanted in the source diffusion layer and source wiring region. After the resist pattern 212 is removed, annealing is performed at high temperature to activate phosphorus ions implanted in the step of FIGS. 4A and 4B and to control the thickness of the source diffusion layer to a level required for ensuring reliability.
As shown in FIGS. 5A and 5B, with the purpose of forming a drain and increasing the concentration of impurities of a source surface, the arsenic ions are implanted in the entire surface including the source wiring region and then activated by heat treatment.
As shown in FIGS. 6A and 6B, using phosphorus having a high diffusion coefficient and high-temperature annealing for diffusion, a source erase type flash EEPROM thus formed will acquire a source diffusion layer formed sufficiently deep to ensure reliability. Furthermore, to make high-density memory cells, the EEPROM is miniaturized in the manufacturing steps by the application of the SAS technology. The resultant structure shown in FIGS. 6A, 6B, and 7 includes phosphorus doped source 213b, phosphorus doped source wiring layer 213c, drain 214a, arsenic doped source 214b, and arsenic doped source wiring layer 214c.
It is possible to introduce phosphorus into the source diffusion layer by using the resist pattern 210 as a mask, in the steps of FIGS. 2A and 2B. In this case, a resist pattern 212 is not required. However, impurities are implanted in the source diffusion layer while the P-type silicon substrate 201 is being exposed, so that heavy metal impurities are introduced into the P-type silicon substrate 201. The heavy metal impurities thus implanted are known to cause a problem with an increase of a junction leak. Therefore, after the mask of the resist pattern 210 is removed, the following procedure is generally taken. That is, the post oxide film 211 is formed; the same resist pattern 212 as the resist pattern 210 is formed; and phosphorus is introduced. In these steps, the post oxide film 211 serves as a mask for blocking a problem of the heavy-metal impurities during phosphorus implantation.
In the source erase type flash EEPROM mentioned above, it is important to prevent an excessive erase and a nonuniform erase. For example, if there is a memory cell erased excessively by the erase operation, the potential of a word line will not elevate. As a result, a fatal defect occurs in that a read/write operation is not carried out. If there is a nonuniform erase, a high speed read/write operation cannot be carried out. In addition, miss writing will occur. Then, in the semiconductor device manufactured in accordance with the aforementioned steps, phosphorus is introduced into the source diffusion layer by ion implantation to form a deep diffusion layer and thereby reducing the electric field component parallel to the interface between the semiconductor substrate and the first gate insulating film during the erase operation. Due to such a construction, the generation of a tunnel current between bands, which has a negative effect on the reliability is prevented.
However, in the aforementioned construction, miniaturization of the memory cells and high-density memory cells required for increasing the capacity cannot be achieved. The reasons will be described below.
First of all, the reliability (as to an excess erase and nonuniform erase) inherent in the EEPROM, will be described briefly. When an oxide film, which has been damaged in the implantation step of phosphorus and arsenic ions for the formation of the source diffusion layer shown in FIGS. 4A, 4B, 5A and 5B, still remains unrecovered from the damage, an F-N current path 217 is generated also in the area other than an area 216 which the F-N current primarily passes through during the erase operation, as shown in FIG. 7. The path thus formed will cause an excessive erase and a nonuniform erase. To prevent the problems during the erase operation, it is necessary to reduce the damage during the ion implantation. To reduce the damage, an underlying oxide film 211 must be prepared thick in preparation for the phosphorus or arsenic ions implantation performed for forming the source diffusion layer. In addition, if the annealing treatment is performed, but insufficient after the implantation step shown in FIGS. 4A and 4B, the diffusion layer will not be formed deep enough to prevent the generation of a tunnel current between bands. Therefore, the annealing must be performed for a long time at high temperature. As a natural consequence, more heat treatment steps are required and the process temperature is also increased. As a result, the channel control of a single layer type transistor element present on the same substrate becomes difficult, with the result that the miniaturization of the single layer type transistor element constituting a peripheral circuit will be inhibited.
On the other hand, if a source diffusion layer is formed deep to improve the reliability of the memory cells, the depth of the diffusion layer of the source wiring area 213c will be increased. In this case, impurities enter into the area right under the field oxide film 203 which separates adjacent drain diffusion layers 214a from each other, increasing the leak between bit lines. The leak is caused by a high potential application, for example, about 7 V and 12.5 V to the bit line and the word line 208 which constitute a cell to be written, respectively. At this time point, a difference in potential is generated between the drain constituting the cell ready for writing and the drain of an adjacent cell having a word line 208 in common. In a conventional memory cell, if the source diffusion layer is uniformly deep, the source diffusion layer enters into part of the surface of the silicon substrate 201 right under the word line 208 and the field oxide film 203. Hence, an inverted layer is likely to appear during a writing operation, increasing the leak between bit lines. To be more specific, a high potential is applied to the drain during the writing operation; however, the potential for writing is decreased by the leak between bit lines. As a result, in some cases, write failure, write error, or data drop occurs. To prevent the leak between bit lines, the width and thickness of the field oxide film 203 interposed between adjacent memory cells must be increased. This is a big obstacle to memory-cell miniaturization. Attempts to miniaturize the memory cells by eliminating the obstacle using the SAS technology almost have reached their limit, at present. Therefore, it is difficult to further increase the memory capacity by the SAS technology.
To increase the capacity of the semiconductor memory, the approaches depending on miniaturizing processing techniques, which attain miniaturization by decreasing the sizes of memory cells and thereby increasing the density thereof, are insufficient. Efforts must be given not only to realize high-density memory cells but also to attain high-speed read/write and erase operations. If not, market requirements will not be satisfied. In addition, the manufacturing cost is increased since it takes a long time for a product to be tested before shipment. As is well known, in the memories such as an EPROM and an EEPROM using a second gate insulating film 207 sandwiched between a floating gate electrode and a control gate electrode, as a capacitance for data storage, if a sufficient capacitance volume of the second gate insulating film 207 is ensured, a high-speed write and high speed erase will be realized, resulting in shortening the test time. Moreover, a high channel current will result which enables a high-speed reading. To ensure the capacitance volume of the second gate insulating film 207, known are only two methods: one is to reduce the thickness of the second gate insulating film 207; and the other is to increase the area of the second insulating film 207. However, the latter method naturally offers a problem in that the memory cells are enlarged.
In the former case, it is necessary to reduce the concentration of impurities present in the polysilicon serving as a material for the floating gate electrode, in advance. The silicon doped with a large amount of impurities exhibits an accelerated oxidation effect, which accelerates an oxidation rate of the silicon. To describe more specifically, in the case where the polysilicon serving as a material for the floating gate electrode is doped with a large amount of impurities, it will be difficult to make a SiO.sub.2 film thin, which is the lowermost layer constituting the second insulating film 207.
However, if the polysilicon 205 serving as the floating gate electrode contains impurities in a low amount, it is known that sharp protrusions appear at a grain corner portion and an etching corner portion due to an oxidation stress during oxidation and heat treatment carried out in the second insulating film 207 formation step, in the post oxidation film 211 formation step, and an annealing step after the phosphorus ion implantation shown in FIGS. 4A and 4B. The protrusion causes the convergence of the electric field, which further causes problems in data storage and in data erase such as an excessive erase and a nonuniform erase.
To explain this more specifically referring to FIG. 7, when the concentration of impurities is low, a sharp protrusion is generated at the corner of the floating gate electrode 205 by the oxidation (heat) stress. In short, not only in the primary F-N current path 216 , but also in the electric-field converged protrusion, the F-N current path 217 is formed. As a result, the nonuniform erase and excessive erase will frequently occur. The only way to prevent the generation of the path is to suppress the protrusion of the corner of the floating gate electrode 205. To suppress the protrusion, a thermal treatment step performed at an extremely high temperature, e.g. 1000.degree. C. is required. However, in this case, it is difficult to miniaturize memory cells, as mentioned previously.